This invention relates to IC testing apparatuses which perform testing on test devices such as integrated circuits (ICs). Particularly, this invention relates to an IC testing apparatus which is capable of adjusting the skew (i.e., time delay) between signals transmitted with respect to test devices.
The skew occurs when transmitting these signals through multiple transmission systems. So, the skew indicates a shift deviated from expected values representing phases which occur between the signals or expected values representing amplitudes of the signals in time. There are 2 kinds of skews, i.e., a driver skew and a comparator skew. The driver skew occurs when a test signal applied to a test device passes through a driver. That is, the driver skew is caused to occur due to errors in characteristics of elements constructing the driver or errors of circuits constructing the driver. The comparator skew occurs when a receiving signal passes through a comparator. Herein, the receiving signal is a signal which is output from the test device and is input to the IC testing apparatus.
FIG. 3 is a block diagram showing an example of the IC testing apparatus. In FIG. 3, skew adjusting circuits 1-1 to 1-n and 2-1 to 2-n delay or advance 1-bit test signals d1 to dn and D1 to Dn respectively. Herein, a test signal forming circuit (not shown) is constructed based on skew correction data, the contents of which will be described later. Drivers 3-1 to 3-n and 4-1 to 4-n are connected in series with the skew adjusting circuits 1-1 to 1-n and 2-1 to 2-n respectively. The drivers convert the test signals to the voltage which matches with a test device.
Comparators 5-1 to 5-n are connected to follow outputs of the drivers 4-1 to 4-n respectively. Each of the comparators performs a comparison between an output signal of the test device and a reference value which is determined in advance on the basis of the voltage matching with the test device. If the output signal of the test device is higher than the reference value, the comparator provides an output of `H` (i.e., a high-level output). Skew adjusting circuits 6-1 to 6-n are configured similar to the aforementioned skew adjusting circuits 1-1 to 1-n and 2-1 to 2-n, wherein they are connected to follow outputs of the comparators 5-1 to 5-n respectively. In addition, the skew adjusting circuits 6-1 to 6-n each receive skew correction data. On the basis of the skew correction data, the skew adjusting circuits 6-1 to 6-n delay or advance output signals of the comparators 5-1 to 5-n respectively.
The test device has multiple signal pins which contain an input pin and an input/output pin. Herein, the input pin is exclusively used for inputting of a signal, whilst the input/output pin is used for inputting and outputting of a signal. The drivers 3-1 to 3-n are connected to the input pin of the test device. The drivers 4-1 to 4-n and the comparators 5-1 to 5-n are connected to the input/output pin of the test device.
A skew multiplexer 10 has multiple lines of input/output terminals, disposed at a left side thereof, as well as a single line of input/output terminals positioned at a right side thereof. The multiple lines of input/output terminals of the skew multiplexer 10 are connected to follow outputs of the drivers 3-1 to 3-n and 4-1 to 4-n. In the skew multiplexer 10, connections are sequentially made between the multiple lines of input/output terminals and the single line of input/output terminals under the control of a central processing unit (i.e., CPU) 15, the content of which will be described later. A driver 11 is configured similarly to the aforementioned drivers 3-1 to 3-n and 4-1 to 4-n. Further, a comparator 12 is configured as similar to the aforementioned comparators 5-1 to 5-n. The single line of input/output terminals of the skew multiplexer 10 is connected to follow an output of the driver 11 as well as an input of the comparator 12.
A decision circuit 13 has two inputs and one output. Herein, a first input of the decision circuit 13 is connected to an output of the comparator 12. In addition, a second input of the decision circuit 13 receives a decision strobe signal which forms a reference in timing for driver signals applied to the test device. The decision strobe signal synchronizes with the test signals input to the skew adjusting circuits 1-1 to 1-n and 2-1 to 2-n. At a leading-edge timing of the decision strobe signal, the decision circuit 13 latches an output signal of the comparator 12 to make a decision on its timing. For example, if the output signal of the comparator 12 is in a high (H) level at the leading-edge timing of the decision strobe signal, the decision circuit 13 provides an output of `H`. In contrast, if the output signal is in a low (L) level, the decision circuit 13 provides an output of `L`. The output of the decision circuit 13 is called a decision signal which represents an event of `pass` if it is `L` or which represents an event of `fail` (or failure) if it is `H`. So, the output of the decision circuit 13 representing `pass` or `fail` is input to an OR circuit 14.
Next, decision circuits 9-1 to 9-n are connected to the skew adjusting circuits 6-1 to 6-n respectively. They are configured similar to the decision circuit 13 described above. So, outputs of the decision circuits 9-1 to 9-n representing `pass` or `fail` are input to the OR circuit 14. The CPU 15 calculates skew correction data based on an output of the OR circuit 14. The skew correction data controls the skew adjusting circuits 1-1 to 1-n, 2-1 to 2-n and 6-1 to 6-n. In addition, the CPU 15 stores the calculated skew correction data in a storage device (not shown) such as a hard-disk unit in a file form. As described before, the CPU 15 is provided to control the skew multiplexer 10. In addition, the CPU 15 performs an overall control on the apparatus as a whole. A skew register unit 16 contains registers which work for the skew adjusting circuits 1-1 to 1-n, 2-1 to 2-n and 6-1 to 6-n respectively. So, the calculated skew correction data are stored in each of the registers.
Next, a description will be given with respect to operations of the apparatus of FIG. 3, which adjusts the driver skew of the test signals applied to the test device, in conjunction with FIGS. 4A to 4L. FIGS. 4A to 4L are time charts representing waveshapes of signals monitored at certain portions of the IC testing apparatus of FIG. 3. The waveshape of FIG. 4A represents each of the test signals d1 to dn and D1 to Dn which are applied to the apparatus. Because of the functions of the skew adjusting circuits 1-1 to 1-n, 2-1 to 2-n, 6-1 to 6-n and the functions of the drivers 3-1 to 3-n, 4-1 to 4-n, the test signal originally represented by the waveshape of FIG. 4A is shifted in timing to form a waveshape of FIG. 4B. In response to the test signals, the drivers 3-1 to 3-n and 4-1 to 4-n provide output signals, each represented by a waveshape of FIG. 4C, whose voltage is converted to match with the test device. Incidentally, FIG. 4C shows an example of the waveshape, representing the output signal of the driver, which is not shifted from the original waveshape of the test signal shown in FIG. 4A.
Only one of the output signals of the drivers 3-1 to 3-n and 4-1 to 4-n is selected by the CPU 15 and is input to the comparator 12 via the skew multiplexer 10. For example, the output signal of the driver 3-1 is firstly selected and is input to the comparator 12; next, the output signal of the driver 3-2 is selected and is input to the comparator 12. The comparator 12 performs comparison between a predetermined reference value thereof and the selected output signal of the driver corresponding to the test signal. Then, a result of the comparison is forwarded to the decision circuit 13. So, the decision circuit 13 latches a value of an output signal of the comparator 12 at a leading-edge timing of the decision strobe signal having a waveshape shown in FIG. 4E. FIG. 4F shows a waveshape of the output signal of the comparator 12.
On the basis of the latched value of the output signal of the comparator 12, the decision circuit 13 produces a decision signal representing `pass` or `fail`. The decision signal is forwarded to the CPU 15 via the OR circuit 14. So, the CPU 15 makes a decision, based on the decision signal which is produced in response to the test signal (e.g., d1), as to whether or not the decision signal delays or advances from the decision strobe signal. If it advances, the CPU 15 calculates skew correction data to instruct `delay`. If it delays, the CPU 15 calculates skew correction data to instruct `advance`.
The calculated skew correction data are stored in the storage device in the file form and are forwarded to the corresponding register of the skew register unit 16. So, the skew adjusting circuit 1-1 sets a delay time or an advance time (see FIGS. 4G and 4H) based on the skew correction data stored in the corresponding register of the skew register unit 16. Thereafter, the CPU 15 gradually changes the skew correction data which are forwarded to the skew register unit 16. Such a gradual change of the skew correction data is continuously made until a transition occurs from `pass` to `fail` (or from `fail` to `pass`) with respect to the decision signal which the decision circuit 13 outputs in response to the selected test signal (i.e., output signal of the selected driver). Such an operation is called a `binary search`. A point of the transition corresponds to a leading-edge timing of a decision strobe signal shown in FIG. 4I. So, the test signals should be matched with the above timing.
After completion of the binary search which the CPU 15 performs with respect to the selected test signal, the CPU 15 issues an instruction to the skew multiplexer 10 to select another test signal. Based on the instruction, the skew multiplexer 10 newly selects a test signal. So, the CPU 15 performs a binary search on the test signal newly selected. Thus, it is possible to adjust the test signal in timing. As described heretofore, the CPU 15 performs the binary search on all of the test signals d1 to dn and D1 to Dn, thus adjusting them in timings.
As a result, all the test signals (i.e., output signals of the drivers 3-1 to 3-n and 4-1 to 4-n) correspond with each other in timings. Thus, it is possible to obtain the test signals which do not have shifts in the skew (see FIGS. 4I and 4K). The CPU 15 obtains final results of the calculations for providing the skew correction data which are forwarded to the skew adjusting circuits 1-1 to 1-n and 2-1 to 2-n to provide the test signals without shifts in the skew. The final results of the skew correction data are stored in the skew register unit 16 and are also stored in the storage unit in the file form. The above process is sequentially performed on the test signals (i.e., output signals of the drivers 3-1 to 3-n and 4-1 to 4-n).
Next, a description will be given with respect to operations to adjust the comparator skew. As described before, the comparator skew occurs when the receiving signal, which is outputted from the test device and is input to the IC testing apparatus, passes through the comparator. At first, a skew adjustment reference signal, which simulates the aforementioned test signal shown in FIG. 4A, is input to the driver 11. The driver 11 converts the skew adjustment reference signal in voltage to match with the test device. So, the skew adjustment reference signal whose voltage is converted to match with the test device is applied to the single line of input/output terminals of the skew multiplexer 10. Under the control of the CPU 15, the skew multiplexer 10 makes connections between the single line of input/output terminals and the multiple lines of input/output terminals respectively. For example, the single line of input/output terminals is firstly connected to the comparator 5-1 and is next connected to the comparator 5-2.
Suppose that the skew adjustment reference signal is input to the comparator 5-1 via the skew multiplexer 10. Herein, the comparator 5-1 compares the skew adjustment reference signal with a predetermined reference value (input thereto). Then, an output of the comparator 5-1 is forwarded to the skew adjusting circuit 6-1 wherein it is delayed or advanced. An output signal of the skew adjusting circuit 6-1 is forwarded to the decision circuit 9-1. The decision circuit 9-1 latches a value of the output signal of the skew adjusting circuit 6-1 at a certain timing of a decision strobe signal input thereto which synchronizes with the reference signal. So, the decision circuit 9-1 makes a decision of `pass` or `fail` on the latched value. Thus, the decision circuit 9-1 produces a decision signal representing `pass` or `fail`, which is forwarded to the OR circuit 14. The CPU 15 calculates skew correction data based on the decision signal outputted from the decision circuit 9-1. The calculated skew correction data are stored in the storage device in the file form and are also stored in a register of the skew register unit 16 which corresponds to the skew adjusting circuit 6-1. So, the CPU 15 performs a binary search as described before. Such a binary search is sequentially performed with respect to outputs of the comparators 5-1 to 5-n. As described before, the skew adjustment reference signal is input to the comparators 5-1 to 5-n respectively at different timings; however, the CPU 15 controls the skew adjusting circuits 6-1 to 6-n to adjust timings to provide output signals. That is, the output signals are provided at a same timing.
The aforementioned example of the IC testing apparatus is designed to perform skew corrections by detecting a transition point of the test signal and skew adjustment reference signal with respect to the leading-edge timing of the decision strobe signal. In the actual measurement of the test device, the test signals d1 to dn and D1 to Dn are continuously provided and are input to the apparatus. So, there is a possibility that jitters occur due to shifts in timings of the signals as shown in FIG. 4L. If the jitters occur, the aforementioned example of the IC testing apparatus cannot specify a timing, within the jitters, to perform a skew correction. This greatly affects the precision of the test signals d1 to dn and D1 to Dn in timings. A frequency of the jitters becomes great with respect to high-frequency signals. In short, the IC testing apparatus suffers from a problem of the jitters.